Statically sceduling communication resources in multiprocessor DSP architectures
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 2 (10586393) , 1046-1051
- https://doi.org/10.1109/acssc.1994.471619
Abstract
In statically scheduled multiprocessors inter-processor communication resources can be scheduled by determining, at compile time, the order in which processors require access to shared resources and enforcing this order at run time. We show how to choose an access order such that, under certain assumptions, imposing that order incurs no performance penalty.<>Keywords
This publication has 7 references indexed in Scilit:
- Scheduling strategies for multiprocessor real-time DSPPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Design and implementation of an ordered memory access architecturePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1993
- Range-chart-guided iterative data-flow graph schedulingIEEE Transactions on Circuits and Systems I: Regular Papers, 1992
- Fast prototyping of datapath-intensive architecturesIEEE Design & Test of Computers, 1991
- Architectures for Statically Scheduled DataflowPublished by Springer Nature ,1991
- Static rate-optimal scheduling of iterative data-flow programs via optimum unfoldingIEEE Transactions on Computers, 1991
- Performance analysis and optimization of VLSI dataflow arraysJournal of Parallel and Distributed Computing, 1987