An analog background calibration technique for time-interleaved analog-to-digital converters
- 1 January 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 33 (12) , 1912-1919
- https://doi.org/10.1109/4.735531
Abstract
No abstract availableThis publication has 27 references indexed in Scilit:
- A 12 b 128 MSample/s ADC with 0.05 LSB DNLPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 15-b, 5-Msample/s low-spurious CMOS ADCIEEE Journal of Solid-State Circuits, 1997
- Background digital calibration techniques for pipelined ADCsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1997
- A 10-b 20-Msample/s low-power CMOS ADCIEEE Journal of Solid-State Circuits, 1995
- A 13-b 10-Msample/s ADC digitally calibrated with oversampling delta-sigma converterIEEE Journal of Solid-State Circuits, 1995
- A 10 b, 20 Msample/s, 35 mW pipeline A/D converterIEEE Journal of Solid-State Circuits, 1995
- Comparison of DC offset effects in four LMS adaptive algorithmsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1995
- Linearizing average transfer characteristics of ideal ADC's via analog and digital ditherIEEE Transactions on Instrumentation and Measurement, 1994
- The Design of High-Performance Analog Circuits on Digital CMOS ChipsIEEE Journal of Solid-State Circuits, 1985
- An algorithmic analog-to-digital converterPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1977