The first IA-64 microprocessor: a design for highly-parallel execution
- 7 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 2 references indexed in Scilit:
- A 0.35 μm CMOS 3-880 MHz PLL N/2 clock multiplier and distribution network with low jitter for microprocessorsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Skew-tolerant domino circuitsIEEE Journal of Solid-State Circuits, 1997