An accurate simulation technique for short-circuit power dissipation based on current component isolation
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1157-1161 vol.2
- https://doi.org/10.1109/iscas.1989.100558
Abstract
A circuit simulation technique is presented which permits the measurement of the average short-circuit power dissipation component in integrated circuits. This technique is most appropriate for low-power circuit design and can be applied effectively to any complementary circuit structure, such as CMOS, that does not permit current flow (other than leakage current) during steady-state operation. Short-circuit power dissipation expressions are derived, and SPICE simulation results for a differently ratioed W/sub p//W/sub n/ circuit are shown.Keywords
This publication has 3 references indexed in Scilit:
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