Incoming inspection of FPGA's

30 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 371-377
https://doi.org/10.1109/etc.1993.246578

Abstract

A fault free field programmable array (FPGA) is essential for prototyping design. The authors present a test method that will allow a designer to quickly and efficiently test the FPGA so that he can with confidence know that any errors are design errors and are not due to the presence of manufacturing faults in the FPGA. The fault method is based on a divide and conquer approach for testing regular arrays and allows one to generate test vectors with high fault coverage very efficiently.

Keywords

INSPECTION
FIELD PROGRAMMABLE GATE ARRAYS
CIRCUIT FAULTS
PROTOTYPES
LOGIC ARRAYS
CIRCUIT TESTING
DESIGN ENGINEERING
COMPUTER SCIENCE
PULP MANUFACTURING
APPLICATION SPECIFIC INTEGRATED CIRCUITS

This publication has 2 references indexed in Scilit:

Testing regular arrays: the boundary problem
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
Easily Testable Iterative Systems
IEEE Transactions on Computers, 1973