The superthreaded architecture: thread pipelining with run-time data dependence checking and control speculation
- 24 December 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableThis publication has 14 references indexed in Scilit:
- An Elementary Processor Architecture with Simultaneous Instruction Issuing from Multiple ThreadsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Limits of Control Flow on ParallelismPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- MASA: a multithreaded processor architecture for parallel symbolic computingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Simultaneous multithreading: Maximizing on-chip parallelismPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- The M-Machine multicomputerPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1995
- Processor couplingPublished by Association for Computing Machinery (ACM) ,1992
- Limits of instruction-level parallelismPublished by Association for Computing Machinery (ACM) ,1991
- Strategies for achieving improved processor throughputPublished by Association for Computing Machinery (ACM) ,1991
- A variable instruction stream extension to the VLIW architecturePublished by Association for Computing Machinery (ACM) ,1991
- The Tera computer systemPublished by Association for Computing Machinery (ACM) ,1990