Design of Ternary COS/MOS Memory and Sequential Circuits

1 March 1977

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. C-26 (3) , 281-288
https://doi.org/10.1109/tc.1977.1674821

Abstract

Ternary storage elements are realized using ternary operators and fundamental circuits, designed with the COS/MOS integrated circuits. Several ternary flip-flops (tri-flops) are constructed and described in detail: the PZN (set positive, set zero, and set negative), the clocked PZN, the D-type, and the T-type. Ternary shift registers and ring counter are formed by means of these tri-flops. A master-slave T-type tri-flop is used for the construction of a ternary up counter able to count from 0 to 3n using the normal ternary code or from -(3ⁿ-1)/2 to+(3n -1)/2 when the signed-ternary code is employed. With a small modification, a ternary down counter is also constructed. A divide-by-M ternary counter which can be programmed is described. A memory cell is designed for the construction of a ternary random-access-memory array (TRAM). A ternary decoder and encoder are presented to be the elements of a complete ternary read-only memory (TROM). A modified ternary inverter (MTI) is taken as a unit cell of the ternary memory matrix.

Keywords

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