Clocked CMOS calculator circuitry
- 1 December 1973
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 8 (6) , 462-469
- https://doi.org/10.1109/jssc.1973.1050440
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- Clocked CMOS calculator circuitryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- Yield analysis of large integrated-circuit chipsIEEE Journal of Solid-State Circuits, 1972
- Theory and design of MOS capacitor pull-up circuitsIEEE Journal of Solid-State Circuits, 1969
- Cost-size optima of monolithic integrated circuitsProceedings of the IEEE, 1964