Reliability improvements in solder bump processing for flip chips
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 460-469 vol.1
- https://doi.org/10.1109/ectc.1990.122229
Abstract
A plated solder-bump process used for the manufacture of high-reliability flip chips is described. Characterization work done to improve the process manufacturability and the resulting product reliability gains are reviewed. Two detailed studies of the thin-film deposition conditions and the Cu pedestal plating parameters are described. Recommendations implemented as a result of these studies have reduced the bump-interconnect-failure level from a defect rate of approximately 500 p.p.m. to 1.5. This work highlights the need and the benefits of detailed characterization, which results in more robust manufacturing processes and eventually in more reliable product performance.Keywords
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