A methodology for system-level design for verifiability

This publication has 11 references indexed in Scilit:

• System-level fault modeling and test pattern generation with process algebras
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• Representing circuits more efficiently in symbolic model checking
  Published by Association for Computing Machinery (ACM) ,1991
• Translating system specifications to VHDL
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1991
• The Design of Communicating Systems
  Published by Springer Nature ,1991
• STATEMATE: a working environment for the development of complex reactive systems
  IEEE Transactions on Software Engineering, 1990
• Predicate/Transition Nets
  Published by Springer Nature ,1987
• Automatic Verification of Sequential Circuits Using Temporal Logic
  IEEE Transactions on Computers, 1986
• CIRCAL and the representation of communication, concurrency, and time
  ACM Transactions on Programming Languages and Systems, 1985
• Testing equivalences for processes
  Theoretical Computer Science, 1984
• Design for Testability—A Survey
  IEEE Transactions on Computers, 1982