A flexible multi-port RAM compiler for datapath
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 16.5/1-16.5/4
- https://doi.org/10.1109/cicc.1990.124754
Abstract
A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0- mu m CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32 K three-port RAM and 16 K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kbit) and 10.0 ns (32 kbit), for example.Keywords
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