MorphoSys: an integrated reconfigurable system for data-parallel and computation-intensive applications

Top Cited Papers

1 May 2000

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers

Vol. 49 (5) , 465-481
https://doi.org/10.1109/12.859540

Abstract

This paper introduces MorphoSys, a reconfigurable computing system developed to investigate the effectiveness of combining reconfigurable hardware with general-purpose processors for word-level, computation-intensive applications. MorphoSys is a coarse-grain, integrated, and reconfigurable system-on-chip, targeted at high-throughput and data-parallel applications. It is comprised of a reconfigurable array of processing cells, a modified RISC processor core, and an efficient memory interface unit. This paper describes the MorphoSys architecture, including the reconfigurable processor array, the control processor, and data and configuration memories. The suitability of MorphoSys for the target application domain is then illustrated with examples such as video compression, data encryption and target recognition. Performance evaluation of these applications indicates improvements of up to an order of magnitude (or more) on MorphoSys, in comparison with other systems.

Keywords

COMPUTER APPLICATIONS

This publication has 23 references indexed in Scilit:

HiPCrypto: a high-performance VLSI cryptographic chip
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
Configurable computing: the catalyst for high-performance architectures
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
A dynamic instruction set computer
Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
V830R/AV: embedded multimedia superscalar RISC processor
IEEE Micro, 1998
FPGA and CPLD architectures: a tutorial
IEEE Design & Test of Computers, 1996
Design and implementation of the ‘Tiny RISC’ microprocessor
Microprocessors and Microsystems, 1992
VLSI architecture for block-matching motion estimation algorithm
IEEE Transactions on Circuits and Systems for Video Technology, 1992
Fast algorithms for computing the discrete cosine transform
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1992
A reconfigurable multiprocessor IC for rapid prototyping of algorithmic-specific high-speed DSP data paths
IEEE Journal of Solid-State Circuits, 1992
A family of VLSI designs for the motion compensation block-matching algorithm
IEEE Transactions on Circuits and Systems, 1989