A GaAs 8×8-bit multiplier/accumulator using JFET DCFL
- 1 August 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 21 (4) , 523-529
- https://doi.org/10.1109/jssc.1986.1052566
Abstract
No abstract availableKeywords
This publication has 7 references indexed in Scilit:
- Comparison of the orientation effect of SiO2- and Si3N4-encapsulated GaAs MESFET'sIEEE Electron Device Letters, 1985
- A GaAs 12 × 12 bit expandable parallel multiplier LSI using sidewall-assisted closely-spaced electrode technologyPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1984
- A GaAs 16x16 bit parallel multiplierIEEE Journal of Solid-State Circuits, 1983
- A high-speed LSI GaAs 8x8 bit parallel multiplierIEEE Journal of Solid-State Circuits, 1982
- Analysis of GaAs FET's for integrated logicIEEE Transactions on Electron Devices, 1980
- Radiation Effects in Gaas Junction Field-Effect TransistorsIEEE Transactions on Nuclear Science, 1980
- A device model for an ion-implanted MESFETIEEE Transactions on Electron Devices, 1979