Systolic routing hardware: performance evaluation and optimization
- 1 March 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 7 (3) , 397-410
- https://doi.org/10.1109/43.3173
Abstract
No abstract availableKeywords
This publication has 10 references indexed in Scilit:
- A new routing algorithm and its hardware implementationPublished by Association for Computing Machinery (ACM) ,1986
- Hardware acceleration of gate array layoutPublished by Association for Computing Machinery (ACM) ,1985
- A Class of Cellular Architectures to Support Physical Design AutomationIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1984
- Wire-routing machines—New tools for VLSI physical designProceedings of the IEEE, 1983
- Hardware support for automatic routingPublished by Association for Computing Machinery (ACM) ,1982
- Global wiring on a wire routing machinePublished by Association for Computing Machinery (ACM) ,1982
- An efficient variable-cost maze routerPublished by Association for Computing Machinery (ACM) ,1982
- A Parallel Bit Map Processor Architecture for DA AlgorithmsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981
- The cytocomputerPublished by Association for Computing Machinery (ACM) ,1980
- The Lee Path Connection AlgorithmIEEE Transactions on Computers, 1974