A run-time reconfigurable engine for image interpolation
- 27 November 2002
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Custom Computing Machines (CCM's) have demonstrated significant performance advantages over general-purpose processors for certain classes of problems. However, problems can always be found which require computational resources in excess of those available on a particular CCM. Exploiting the reconfigurable nature of FPGAs can alleviate this limitation. The FPGAs' computational resources can be time multiplexed to allow different portions of the computation to execute in stages. Intermediate results are saved to memory and passed on to later stages of the computation. This technique is used in this work to implement an image interpolation engine on the Xilinx XC6264 Reference Board. The engine utilizes 2-5-2 splines to take advantage of their computationally convenient powers-of-two arithmetic.Keywords
This publication has 4 references indexed in Scilit:
- A dynamic reconfiguration run-time systemPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- An efficient spline basis for multi-dimensional applications: image interpolationPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design methodologies for partially reconfigured systemsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- FPGA applications in digital video systemsPublished by SPIE-Intl Soc Optical Eng ,1996