A VLSI array for computing the DFT based on RNS
- 23 March 2005
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 11, 2147-2150
- https://doi.org/10.1109/icassp.1986.1169308
Abstract
No abstract availableKeywords
This publication has 6 references indexed in Scilit:
- An efficient VLSI adder for DSP architectures based on RNSPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Multi-look-up-table module for RNS systems implementationElectronics Letters, 1984
- Models for VLSI implementation of residue number system arithmetic modulesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1983
- Why systolic architectures?Computer, 1982
- A Cordic Arithmetic Processor ChipIEEE Transactions on Computers, 1980
- Multiplication Using Logarithms Implemented with Read-Only MemoryIEEE Transactions on Computers, 1975