An Algorithm for Determining Minimal Representations of a Logic Function
- 1 June 1957
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electronic Computers
- Vol. EC-6 (2) , 103-108
- https://doi.org/10.1109/tec.1957.5221580
Abstract
For each logic function, or Boolean algebraic expression, there corresponds an appropriate computer circuit. However, the minimization of the appearances of the Boolean variables does not necessarily lead to the most economical circuit. A general approach to the problem therefore requires the development of techniques for the simple and rapid generation of a variety of near-minimal forms. This paper describes such a method for constructing the minimal representations of a logic function given as a truthtable or in one of its canonical forms. The minimal representations achieved are either sums of products, or products of sums, such that no term contains superfluous variables and such that no term is superfluous. The utility of the method lies in the conciseness of notation, which permits the handling of a large number of variables and simplifies the process for machine computation.Keywords
This publication has 1 reference indexed in Scilit:
- The map method for synthesis of combinational logic circuitsTransactions of the American Institute of Electrical Engineers, Part I: Communication and Electronics, 1953