Transport processes of electrons in MNOS structures

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Abstract
The transport processes of electrons in MNOS structures, especially in the SiO2 layer and the surface region of the Si substrate, have been investigated using p‐channel MNOS transistors with a relatively thick SiO2 layer to avoid the complexity of two‐carrier transport in the system. An induced junction technique utilizing the electron and hole separation properties of the transistor structure was used as a means of analysis. Theoretical derivation of the carrier multiplication factor, i.e., the number of electron‐hole pairs produced by an electron entering the Si from the SiO2, is calculated. It is experimentally shown that an electron entering the Si from the SiO2 produces approximately one electron‐hole pair in the low negative gate bias voltage range up to a critical voltage, and above this critical voltage the multiplication factor increases with increasing gate bias voltage. The former observation is in good agreement with the prediction of the theory, considering cascaded impact ionization of an electron with high energy in Si. The latter fact reveals that electrons in SiO2 become hot in the high voltage range. The critical voltage coincides with the value theoretically estimated using an LO phonon energy of 0.153 eV and an electron‐phonon scattering length of 1.74 Å in SiO2. The mean free path of the electrons between scatterings by defects or other scattering centers in SiO2 is estimated to be about 30 Å by analyzing gate bias dependence of the multiplication phenomena.

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