Automated BIST for sequential logic synthesis
- 1 December 1988
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test of Computers
- Vol. 5 (6) , 22-32
- https://doi.org/10.1109/54.9269
Abstract
An automated built-in self-test (BIST) technique for general sequential logic is described that can be used directly at all levels of testing from device testing through system diagnostics. The technique selectively replaces existing system memory elements with BIST flip-flop cells, which it then connects to form a circular chain. Data are compacted and test patterns are generated simultaneously. The approach has been incorporated in a system for behavioral model synthesis to implement BIST in VLSI devices based on standard cells and in circuit packs based on PLDs, automatically. Seven production VLSI devices have been implemented with this automated BIST approach. Area overhead was between 6% and 19% for a fault coverage of 90%+ with the BIST capability alone.Keywords
This publication has 4 references indexed in Scilit:
- Behavioral model synthesis with ConesIEEE Design & Test of Computers, 1988
- Circular self-test path: a low-cost BIST techniquePublished by Association for Computing Machinery (ACM) ,1987
- Built-in Self Testing of Embedded MemoriesIEEE Design & Test of Computers, 1986
- Experiment to investigate self-testing techniques in VLSIIEE Proceedings G (Electronic Circuits and Systems), 1985