Test Schedules for VLSI Circuits Having Built-In Test Hardware
- 1 April 1986
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-35 (4) , 361-367
- https://doi.org/10.1109/TC.1986.1676771
Abstract
In this correspondence, the concept of a test schema which describes how a test methodology is to execute is introduced. We also introduce the powerful concept of an I path which is used to transfer data unchanged from one place in a circuit to another. The process of embedding a test schema into an actual circuit is described. This produces a test plan for the circuit which specifies the sequence of actions that need to be carried out to execute the test. A theory of test plan execution overlap is presented, and is used as the basis for constructing test schedules with optimal execution times.Keywords
This publication has 7 references indexed in Scilit:
- Test Schedules for VLSI Circuits Having Built-In Test HardwareIEEE Transactions on Computers, 1986
- A Knowledge-Based System for Designing Testable VLSI ChipsIEEE Design & Test of Computers, 1985
- Built-In Self-Test TechniquesIEEE Design & Test of Computers, 1985
- A Knowledge Based System for Selecting a Test Methodology for a PLAPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1985
- Design for Testability—A SurveyIEEE Transactions on Computers, 1982
- Testing Logic Networks and Designing for TestabilityComputer, 1979
- Graph Theory with ApplicationsPublished by Springer Nature ,1976