FET power performance prediction using a linearized device model
- 13 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 28, 569-572
- https://doi.org/10.1109/mwsym.1989.38791
Abstract
An analytic model has been developed which, based on a linearized device model, describes the power output at 1-dB gain compression, optimum load impedance, and load-pull contours of a field-effect transistor (FET) explicitly in terms of device parameters. Applications of the model to practical devices including commercial metal-semiconductor FETs and a 0.25- mu m-gate modulation-doped FET showed agreement with measurements to 40 GHz.Keywords
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