Automated data path synthesis to avoid global interconnects
- 1 January 1991
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
Incorporates into a behavioral synthesis system an algorithm to minimize global interconnects in the data path. In order to accomplish this, the authors define a model of the data path to almost completely avoid global interconnects. In this approach, they pay the penalty of extra registers and extra microinstructions to avoid global interconnects. The proposed model of the data path results in large area savings in behavioral synthesis.Keywords
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