A 40-ns 64-Mb DRAM with 64-b parallel data bus architecture
- 1 January 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 26 (11) , 1493-1497
- https://doi.org/10.1109/4.98963
Abstract
No abstract availableKeywords
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- A 64Mb DRAM With Meshed Power Line And Distributed Sense-amplifier DriverPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1991
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- An Experimental 16mb Dram with Transposed Data-Line StructurePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988