A normalized-area measure for VLSI layouts

journal article
Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Vol. 7 (3) , 411-419
https://doi.org/10.1109/43.3174

Abstract

A figure of merit called normalized-area, is introduced for the purpose of evaluating layouts for VLSI networks. This measure is distinctly different from the existing VLSI measures in two major aspects: (1) it expresses the utilization of the layout area by revealing the constant factor hidden in its asymptotic area-complexity; and (2) it distinguishes between node and wire sizes. Normalized-area is valuable in evaluating alternative layouts for a given structure as well as in analyzing the area utilization of a particular layout for that structure in an absolute sense. An analysis of the normalized-area of the layout schemes for regular structures proposed in the literature shows that most of these schemes are infeasible in practice. Array realizations for several well-known regular structures are used to demonstrate the usefulness of the normalized-area measure. Some practical guidelines for placement and routing to achieve good area utilization in a VLSI chip are presented

Keywords

This publication has 7 references indexed in Scilit:

An Array Layout Methodology for VLSI Circuits
IEEE Transactions on Computers, 1986
Complete Binary Spanning Trees of the Eight Nearest Neighbor Array
IEEE Transactions on Computers, 1985
A framework for solving VLSI graph layout problems
Journal of Computer and System Sciences, 1984
Embedding Tree Structures in VLSI Hexagonal Arrays
IEEE Transactions on Computers, 1984
How to assemble tree machines (Extended Abstract)
Published by Association for Computing Machinery (ACM) ,1982
The cube-connected cycles: a versatile network for parallel computation
Communications of the ACM, 1981
Bounds on minimax edge length for complete binary trees
Published by Association for Computing Machinery (ACM) ,1981