VLSI implementation of an entropy coder and decoder for advanced TV applications
- 4 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 3030-3033
- https://doi.org/10.1109/iscas.1990.112650
Abstract
Experimental prototype high-speed entropy coder and decoder chips with parallel architectures are discussed. Two coding techniques, run-length coding and variable-length coding, are implemented in these two chips. Designed in a 1.2- mu m double-metal CMOS technology, the die-size of each chip is about 5 mm*5 mm. Each chip contains about 35 K transistors. Based on the simulation of critical parts, they are expected to meet a speed objective of 52 MHz with margin.Keywords
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