Using SEMATECH Electrical Test Structures in Assessing Plasma Induced Damage in Poly Etching
- 1 July 1994
- journal article
- Published by IOP Publishing in Japanese Journal of Applied Physics
- Vol. 33 (7S)
- https://doi.org/10.1143/jjap.33.4458
Abstract
The use of capacitive antenna structures to assess process-induced charging damage is well documented. A description of a subset of the SEMATECH process-induced damage effect revealer (SPIDER) module set is given in this report. SPIDER utilizes various sizes and shapes of antenna structures tied to transistors. In this investigation, the evaluation of plasma etch damage, primarily from the gate polysilicon etch, is reported using 0.5 µ m n-channel metal-oxide-semiconductor (NMOS) antenna transistor. Damage appears to occur at the gate oxide bulk and interface. A portion of this damage is not measured after post-metallization annealing unless activated by electrical stress or some subsequent processing. The damage does not correlate with transistor antenna area present during the poly-Si etch. However, a correlation is observed for transistor parameters measured after activation by Fowler-Nordheim stress. This latency may be attributed to hydrogen passivation. A damage model is presented here.Keywords
This publication has 3 references indexed in Scilit:
- Effect of plasma poly etch on effective channel length and hot carrier reliability in submicron transistorsIEEE Electron Device Letters, 1994
- Impact of polysilicon dry etching on 0.5 /spl mu/m NMOS transistor performance: the presence of both plasma bombardment damage and plasma charging damageIEEE Electron Device Letters, 1994
- Thin oxide charging current during plasma etching of aluminumIEEE Electron Device Letters, 1991