A new approach to analyze interconnect delays in RC wire models
- 20 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- Vol. 6, 246-249
- https://doi.org/10.1109/iscas.1999.780141
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
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- CMOS scaling for high performance and low power-the next ten yearsProceedings of the IEEE, 1995
- Asymptotic waveform evaluation for timing analysisIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1990
- The modeling of resistive interconnects for integrated circuitsIEEE Journal of Solid-State Circuits, 1983