Test efficiency analysis of random self-test of sequential circuits
- 1 March 1991
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
- Vol. 10 (3) , 390-398
- https://doi.org/10.1109/43.67792
Abstract
No abstract availableKeywords
This publication has 3 references indexed in Scilit:
- Circular self-test path: a low-cost BIST technique for VLSI circuitsIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
- On using signature registers as pseudorandom pattern generators in built-in self-testingIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1988
- Tables for the Solution of the Exponential Equation, exp(-a) + ka = 1Biometrika, 1960