High breakdown voltage MESFET with planar gate structure for low distortion power applications
- 30 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 181-184
- https://doi.org/10.1109/gaas.1993.394474
Abstract
A high gate-drain breakdown voltage (V/sub BD/) MESFET with low distortion characteristics was successfully demonstrated. A 0.7 /spl mu/m MESFET with a planar gate structure achieved as high as V/sub BD/ of -19 V with a standard deviation of 2.6 V in a three-inch-diameter GaAs wafer. Power performances evaluated at a 9 V drain bias and 1/2 Idss0 for a 4.8-mm gate periphery device demonstrated a 1 dB compression power (P/sub 1dB/) of 34 dBm with a 47.9% power-added efficiency at 1.5 GHz in A-class operation. A third-order intercept point (IP/sub 3/) of 42 dBm was evaluated at a 4.5 V drain bias and 0.4 Idss0 on a 500 /spl mu/m device at 1.5 GHz. A linearity figure-of-merit of 40.8 was recorded.<>Keywords
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