Architecture and evaluation of a high-speed networking subsystem for distributed-memory systems
- 17 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
No abstract availableKeywords
This publication has 16 references indexed in Scilit:
- The Touchstone 30 Gigaflop DELTA PrototypePublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- The Assign Parallel Program GeneratorPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2005
- Supporting systolic and memory communication in iWarpPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A programmable HIPPI interface for a graphics supercomputerPublished by Association for Computing Machinery (ACM) ,1993
- High speed networking at Cray researchACM SIGCOMM Computer Communication Review, 1991
- A new approach for automatic parallelization of blocked linear Algebra computationsPublished by Association for Computing Machinery (ACM) ,1991
- Supercomputing with transputers—past, present and futurePublished by Association for Computing Machinery (ACM) ,1990
- Processing element design for a parallel computerIEEE Micro, 1990
- An analysis of TCP processing overheadIEEE Communications Magazine, 1989
- A Microprocessor-based Hypercube SupercomputerIEEE Micro, 1986