An improved input protection circuit for C-MOS/SOS arrays
- 1 August 1978
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 25 (8) , 926-932
- https://doi.org/10.1109/t-ed.1978.19203
Abstract
A protective network for silicon-gate C-MOS/SOS arrays has been designed that is capable of protecting input circuits from static discharges in excess of 2200 V. This paper describes the results of a program undertaken at RCA to develop a protection network for C-MOS arrays on sapphire substrates capable of withstanding 1500-v static discharges. A test chip with eight input protection configurations was designed, processed, and tested. The results were incorporated into a network design that exceeds the requirements without degrading circuit speed.Keywords
This publication has 1 reference indexed in Scilit:
- Hybrid Protective Device for MOS-LSI ChipsIEEE Transactions on Parts, Hybrids, and Packaging, 1976