A fast and efficient algorithm for determining fanout trees in large networks
- 9 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 539-544
- https://doi.org/10.1109/edac.1991.206466
Abstract
This paper presents a heuristic algorithm to the optimal selection of the fanout tree structures in VLSI circuit design. The algorithm minimizes area of the added buffers under the specified timing constraints. The algorithms described in the literatures [11], [12], [13]solve a simpler problem of minimizing the circuit's timing without taking into account the area increase introduced by the buffers. Experimental results demonstrate that our approach is very fast and efficient, particularly for large examples whose solution spaces are very large.Keywords
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