Bipolar transistor scaling for minimum switching delay and energy dissipation
- 6 January 2003
- proceedings article
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
A novel figure-of-merit to guide in the scaling of high-speed bipolar transistors is proposed. A method is described to relate the gate delay of a ring-oscillator to measurable device parameters analytically. The closed-form solution for an unloaded ECL (emitter coupled logic) gate agrees very well with published data of the past several years and with the results of circuit simulation. The formula for the basic current switch relates in a simple way the different device parameters and has been used to optimize device design for maximum speed and minimum energy dissipation.Keywords
This publication has 5 references indexed in Scilit:
- Figure of merit for integrated bipolar transistorsSolid-State Electronics, 1986
- Analytic approximations for propagation delays in current-mode switching circuits including collector-base capacitancesIEEE Journal of Solid-State Circuits, 1981
- Bipolar transistor design for optimized power-delay logic circuitsIEEE Journal of Solid-State Circuits, 1979
- A distributed model of the junction transistor and its application in the prediction of the emitter-base diode characteristic, base impedance, and pulse response of the deviceIEEE Transactions on Electron Devices, 1965
- The method of estimating delay in switching circuits and the figure of merit of a switching transistorIEEE Transactions on Electron Devices, 1964