Boolean satisfiability and equivalence checking using general binary decision diagrams

This publication has 8 references indexed in Scilit:

• Ordered binary decision diagrams and circuit structure
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Logic verification using binary decision diagrams in a logic synthesis environment
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Evaluation and improvement of Boolean comparison method based on binary decision diagrams
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2003
• Efficient implementation of a BDD package
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,2002
• On the complexity of VLSI implementations and graph representations of Boolean functions with application to integer multiplication
  IEEE Transactions on Computers, 1991
• Using BDDs to verify multipliers
  Published by Association for Computing Machinery (ACM) ,1991
• Graph-Based Algorithms for Boolean Function Manipulation
  IEEE Transactions on Computers, 1986
• Logic Minimization Algorithms for VLSI Synthesis
  Published by Springer Nature ,1984