Tree Realizations of Iterative Circuits
- 1 April 1977
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-26 (4) , 365-383
- https://doi.org/10.1109/TC.1977.1674846
Abstract
It is shown how any combinational function that can be described by a flow table—or equivalently—is realizable in iterative form—can be realized in tree form. The propagation delay is then proportional to the logarithm of n, the number of inputs, while the logic complexity is a linear function of n. These results are related to various implementations of high-speed binary adders and a proposed new high-speed adder circuit.Keywords
This publication has 3 references indexed in Scilit:
- The Production of Completion Signals by Asynchronous, Iterative NetworksIEEE Transactions on Electronic Computers, 1964
- Skip Techniques for High-Speed Carry-Propagation in Binary Arithmetic UnitsIEEE Transactions on Electronic Computers, 1961
- Conditional-Sum Addition LogicIEEE Transactions on Electronic Computers, 1960