A defect and fault tolerant design of WSI static RAM modules

4 December 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 213-219
https://doi.org/10.1109/icwsi.1990.63903

Abstract

Advanced redundancy configurations of static RAM modules based on word duplication and selection by horizontal parity checking (WDSH), as well as based on error correction by horizontal and vertical parity checking (ECHV), are proposed for enhancement of defect and fault tolerance capability of WSIs. The following additional redundancy technologies are applied to them: word selection by automatic access error checking, pair unit replacement are for WDSH-based configurations using multiple RAM units, and two-level hierarchical redundancy is for ECHV-based ones. Performance estimation using a 1.5-micron 128 K-bit CMOS static RAM module model indicates that a remarkably higher degree of effective active area reduction, in respect to defect and fault occurrence, can be attained by an optimum WDSH-based configuration than by a general triplication-based redundancy configuration Author(s) Tsuda, N. NTT Commun. & Inf. Process. Labs., Kanagawa, Japan

Keywords

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