Fail-Safe Asynchronous Sequential Machines
- 1 June 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. C-24 (6) , 675-677
- https://doi.org/10.1109/t-c.1975.224282
Abstract
Fail-safe circuits are designed to assume a 1 (1-fail-safe) or a 0 (0-fail-safe) output state upon failure. This correspondence extends fault detection techniques previously presented [1] to include the design of fail-safe asynchronous sequential circuits. Faults causing failures in the internal state logic and the output state logic circuitry are treated. These failures are assumed to be symmetric and the resulting circuit realizations require less hardware than realizations derived from previously presented techniques.Keywords
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