Opens board test coverage: when is 99% really 40%?
- 24 December 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 333-339
- https://doi.org/10.1109/test.1996.556979
Abstract
In this paper we discuss board test coverage of opens for power pins of large ASICs soldered to electronic boards. Multiple power pin connections cannot be tested by typical electrical testing techniques because they are connected in parallel between the package and the board. We present in this paper an estimate of the probability of these power pin opens, outline the impact of the lack of test coverage in system performance, and offer possible solutions to the problem,.Keywords
This publication has 5 references indexed in Scilit:
- Testing multiple power connections with boundary scanPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2003
- Structure and metrology for an analog testability busPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Defects, fault coverage, yield and cost, in board manufacturingPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- Design at the system level with VLSI CMOSIBM Journal of Research and Development, 1995
- The Boundary-Scan HandbookPublished by Springer Nature ,1992