A time-multiplexed FPGA architecture for logic emulation
- 19 November 2002
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 495-498
- https://doi.org/10.1109/cicc.1995.518231
Abstract
This paper presents an architecture for a FPGA oriented towards logic emulation, to achieve maximum usable logic density per unit silicon area, and fast mapping. Logic circuits are translated into a program that is executed sequentially by a network of processor elements. Overall, a sevenfold increase in raw logic blocks, and a 25-fold increase in usable logic blocks compared to a FPGA-based logic emulator is expected for a given silicon area.Keywords
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