A reconfigurable VLSI coprocessing system for the block matching algorithm
- 1 September 1997
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 5 (3) , 329-337
- https://doi.org/10.1109/92.609876
Abstract
Several VLSI architectures for the full-search block matching algorithm have been proposed in recent years due to its computation and I/O-intensive nature and its importance in various computer vision and image processing applications. This paper presents a new coarse grained reconfigurable coprocessor which is suitable for integration with general purpose microprocessors. The 180000 transistor custom VLSI design was implemented in 0.6 /spl mu/m CMOS on a 4.12 min/spl times/2.59 mm die and has been fully tested up to 33 MHz. For a typical image database search application, a sample system consisting of four coprocessors interfaced through a 33 MHz PCI bus will provide a speedup of 320/spl times/ over an 80486 DX2/66 MHz and 64/spl times/ over a 150-MHz Pentium running fully optimized assembly code.Keywords
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