Design process model in the Yorktown silicon compiler
- 6 January 2003
- conference paper
- Published by Institute of Electrical and Electronics Engineers (IEEE)
Abstract
The automatic synthesis of an IBM 801 processing unit using the Yorktown silicon compiler is presented. The underlying design process model is explained showing the intermediate stages, while emphasizing high-level issues. First, the principles of operations are translated manually into high-level behavioral descriptions. The system is decomposed by the designer into concurrent modules (in the 801, four pipeline stages). Structural synthesis automatically generates a circuit structure for each pipeline stage, including the control and the data path. The combinational logic is optimized globally during logic synthesis producing a multilevel implementation. The resulting size (in number of transistors) and the performance of the processor (estimated cycle time and cycles per instruction) are compared to a manual RT-level design.Keywords
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