ACE4k: An analog I/O 64×64 visual microprocessor chip with 7‐bit analog accuracy

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Abstract
This paper describes a full‐custom mixed‐signal chip which embeds distributed optical signal acquisition, digitally‐programmable analog parallel processing, and distributed image memory cache on a common silicon substrate. This chip, designed in a 0.5 µm standard CMOS technology contains around 1.000.000 transistors, of which operate in analog mode; it is hence one the most complex mixed‐signal chip reported to now. Chip functional features are: local interactions, spatial‐invariant array architecture; programmable local interactions among cells; randomly‐selectable memory of instructions (elementary instructions are defined by specific values of the cell local interactions); random storage/retrieval of intermediate images; capability to complete algorithmic image processing tasks controlled by the user‐selected stored instructions and interacting with the cache memory, etc. Thus, as illustrated in this paper, the chip is capable to complete complex spatio‐temporal image processing tasks within short computation time (<300 ns for linear convolutions) and using a low power budget (7‐bits equivalent accuracy in the internal analog operations, which has been confirmed by experimental measurements. Such 7‐bits accuracy is enough for most image processing applications. ACE4k has been demonstrated capable to implement up to 30 templateσ‐either directly or through template decomposition. This means the 100% of the 3×3 linear templates reported in Roska et al. 1998, [1]. Copyright © 2002 John Wiley & Sons, Ltd.

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