A simple charge regenerator for use with charge-transfer devices and the design of functional logic arrays

Abstract
An inverting binary-charge regenerator for use with new charge- transfer devices (charge-coupled and integrated MOS bucket brigade) is described. This simple element requires an area approximately that of one bit in the register and is driven by the transfer pulses. Its uses with these shift registers in various configurations, which are described, make possible even larger functional devices. These uses include regeneration in serial memories, performing logic operations such as NAND and NOR involving the bit trains in several registers, and performing fixed counts and sequential addressing of other circuit elements.

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