A low power and high speed data transfer scheme with asynchronous compressed pulse width modulation for AS-memory

19 November 2002

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

p. 27-28
https://doi.org/10.1109/vlsic.1995.520672

Abstract

We propose a high speed and low power data transfer scheme for the wide internal data bus of an AS-Memory using the asynchronous compressed pulse width modulation (AC-PWM) technique and an automatic gain controlled (AGC) amplifier. The maximum bit rate per bus of AC-PWM increases by 12 times that of the conventional 100MHz data bus. The AGC amplifier achieves a fast data output while reducing by 1/3 the standby current. The proposed architecture is a key advance in the future development of AS-Memories.

Keywords

PULSE WIDTH MODULATION
PULSE COMPRESSION METHODS
SPACE VECTOR PULSE WIDTH MODULATION
PULSE AMPLIFIERS
CIRCUITS
ENERGY CONSUMPTION
DELAY
READ ONLY MEMORY
TIMING
DEMODULATION

This publication has 1 reference indexed in Scilit:

A 100-MHz 4-Mb cache DRAM with fast copy-back scheme
IEEE Journal of Solid-State Circuits, 1992