Clocking Links in Multi-chip Packages: A Case Study

1 August 2010

conference paper
Published by Institute of Electrical and Electronics Engineers (IEEE)

No. 15504794,p. 96-103
https://doi.org/10.1109/hoti.2010.18

Abstract

This brief note presents a case study for clocking links in multi-chip packages. A particular co-packaged multichip system design based on multi-Gbps silicon photonics global interconnect provides the context for our study of near-short range links, and we explore its design space. A preliminary exploration of phase noise suggests that the links should be clocked mesochronously, with an optically distributed full-rate clock and using local phase adjustment at each receiver.

Keywords

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