The impact of scaling down to deep submicron on CMOS RF circuits
- 1 July 1998
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 33 (7) , 1023-1036
- https://doi.org/10.1109/4.701249
Abstract
No abstract availableKeywords
This publication has 18 references indexed in Scilit:
- A 2.7 V GSM RF transceiver ICPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 12 mW wide dynamic range CMOS front end for a portable GPS receiverPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 2.7 V GSM transceiver ICs with on-chip filteringPublished by Institute of Electrical and Electronics Engineers (IEEE) ,2002
- A 1.57-GHz RF front-end for triple conversion GPS receiverIEEE Journal of Solid-State Circuits, 1998
- A 1 GHz CMOS RF front-end IC for a direct-conversion wireless receiverIEEE Journal of Solid-State Circuits, 1996
- A 2.7-V 900-MHz CMOS LNA and mixerIEEE Journal of Solid-State Circuits, 1996
- A single-chip 900 MHz CMOS receiver front-end with a high performance low-IF topologyIEEE Journal of Solid-State Circuits, 1995
- A 1-GHz BiCMOS RF front-end ICIEEE Journal of Solid-State Circuits, 1994
- Enhancement source-coupled logic for mixed-mode VLSI circuitsIEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, 1992
- A 30-MHz hybrid analog/digital clock recovery circuit in 2- mu m CMOSIEEE Journal of Solid-State Circuits, 1990