SrTiO3 thin films by mocvd for 1 gbit DRAM application

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Abstract
Three important aspects of the preparation of SrTiO3 thin films by MOCVD are discussed in detail in view of the application of these films as the capacitor dielectric of Gbit-scale DRAMs: CVD reactions in the Sr(DPM)2-Ti(i-OC3H7)4-O2 system, step coverage and relations between microstructure and electrical properties. The effect of the substrate temperature on the Sr and Ti deposition rates was first investigated for thermal and ECR CVD SrTiO3 films. SrO and TiO2 deposition by thermal CVD above 550°C were found to be controlled by the surface reaction and gas transport, respectively, whereas both SrO and TiO2 deposition are controlled by gas transport for ECR CVD at 450 to 600°C. The influence of the Sr and Ti deposition regimes on the step coverage of SrO, TiO2 and SrTiO3 were then assessed. SrO films prepared by thermal CVD at 600°C exhibited the best step coverage, indicating that a relation exists between reaction controlled deposition and good step coverage. The effect of the film composition and film thickness on the microstructure of SrTiO3 thin films were finally investigated and correlations were made to other analyzed physical and electrical properties. Polycrystalline perovskite phase SrTiO3 films were obtained for a composition 0.7 ≤ Sr/Ti ≤ 1.2. The best crystallinity, maximum permittivity and maximum refractive index were obtained for Sr/Ti = 0.95. Titanium rich films are thought to be composed of a mixture of a titanium rich amorphous phase and crystalline SrTiO3, and strontium rich films are believed top correspond to a (SrTiO3)m (SrO)n structure. The dielectric constant slowly decreased as the film thickness was reduced. The sharp decrease observed near 400–500 Å could be due to the existence of some perturbed layer at the interface with one or both of the electrodes