A 1024-bit MNOS RAM using avalanche-tunnel injection
- 1 October 1975
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 10 (5) , 288-293
- https://doi.org/10.1109/jssc.1975.1050613
Abstract
MNOS memory cells which consist of one MNOS transistor and two MOS transistors are incorporated into a fully decoded 1024-word by 1-bit random access memory (RAM) with nonvolatility. The features of the present nonvolatile RAM are: 1) by introducing a novel mode of write operation, electrical isolators, such as p-n junction isolation between the memory cells and the other circuits are not required, 2) stored data can last more than one year without any kind of external power supply, 3) the chip size of the memory is 3.60/spl times/3.61 mm/SUP 2/, 4) the read-access time is 600 ns and the write cycle time is 10 /spl mu/s-100 /spl mu/s.Keywords
This publication has 6 references indexed in Scilit:
- Fully decoded MNOS storage arrays in ESFI MOS technologyIEEE Journal of Solid-State Circuits, 1974
- A content-addressable memory cell with MNOS transistorsIEEE Journal of Solid-State Circuits, 1973
- The light-sensitive MNOS memory transistorIEEE Transactions on Electron Devices, 1973
- CCD and MNOS devices for programmable analog signal processing and digital nonvolatile memoryPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- The drain-source protected MNOS memory device and memory endurancePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1973
- Degradation of MNOS Memory Transistor Characteristics and Failure Mechanism Model8th Reliability Physics Symposium, 1972