New nibbled-page architecture for high-density DRAMs
- 1 January 1989
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of Solid-State Circuits
- Vol. 24 (4) , 900-904
- https://doi.org/10.1109/4.34068
Abstract
No abstract availableKeywords
This publication has 4 references indexed in Scilit:
- An Experimental 16mb Cmos dram Chip with a 100mhz Serial Read/Write ModePublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A new nibbled-page architecture for high density DRAMsPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1988
- A 64K DRAM with 35 ns static column operationIEEE Journal of Solid-State Circuits, 1983
- A 100ns 64K dynamic RAM using redundancy techniquesPublished by Institute of Electrical and Electronics Engineers (IEEE) ,1981