A monolithic 480 Mb/s parallel AGG/decision/clock-recovery circuit in 1.2- mu m CMOS

This publication has 12 references indexed in Scilit:

• A single-chip 266 Mb/s CMOS transmitter/receiver for serial data communications
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1993
• A monolithic 2.3 Gb/s 100 mW clock and data recovery circuit
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1993
• NMOS IC's for clock and data regeneration in gigabit-per-second optical-fiber receivers
  IEEE Journal of Solid-State Circuits, 1992
• A Monolithic 622Mb/s Clock Extraction Data Retiming Circuit
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1991
• A PLL-based 2.5-Gb/s GaAs clock and data regenerator IC
  IEEE Journal of Solid-State Circuits, 1991
• A 52MHz And 155MHz Clock-recovery PLL
  Published by Institute of Electrical and Electronics Engineers (IEEE) ,1991
• A single-chip bipolar AGC amplifier with large dynamic range for optical-fiber receivers operating up to 3 Gbit/s
  IEEE Journal of Solid-State Circuits, 1989
• A 50-Mbit/s CMOS monolithic optical receiver
  IEEE Journal of Solid-State Circuits, 1988
• A Design and Packaging Technique for a High-Gain, Gigahertz-Band Single-Chip Amplifier
  IEEE Journal of Solid-State Circuits, 1986
• A high-gain GaAs amplifier with an AGC Function
  IEEE Electron Device Letters, 1984